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  • 权利要求
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    • 专利摘要:
    PURPOSE: A nonvolatile semiconductor memory and its manufacturing method are provided to improve the charge retention characteristics, and stabilize read operation using a selection transistor, and increase the operating speed of a peripheral transistor. CONSTITUTION: A nonvolatile semiconductor memory comprises a semiconductor substrate, a first transistor formed on a surface of the semiconductor substrate and including a first gate insulating film and a first gate electrode, and a second transistor formed on the surface of the semiconductor substrate and including a second gate insulating film and a second gate electrode, wherein the first gate insulating film includes a charge storage layer and the second gate insulating film does not include a charge storage layer, and the first and second transistors are isolated by a trench and the charge storage layer in the first transistor does not exist in an element isolation region and exists only below the first gate electrode in an element region is provided.
    公开号:KR20020023116A
    申请号:KR1020010056706
    申请日:2001-09-14
    公开日:2002-03-28
    发明作者:사까가미에이지
    申请人:니시무로 타이죠；가부시끼가이샤 도시바；
    IPC主号:
    专利说明:

    Nonvolatile semiconductor memory device and manufacturing method thereof {NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF}
    [40] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a memory cell having a metal-oxide-nitride-oxide-Si (MONOS) structure using a self-aligned shallow trench isolation (SA-STI) method as an isolation method. It is about suitable things.
    [41] Recently, a cell having a MONOS structure has been proposed as a memory cell of an electrically writeable / erasable nonvolatile semiconductor memory device (flash EEPROM).
    [42] FIG. 14 illustrates a longitudinal cross section around a gate electrode of a conventional MONOS memory cell, and FIG. 15 illustrates a vertical cross section around a channel region.
    [43] An n-type well 8 is formed on the surface portion of the p-type semiconductor substrate 9, a p-type well 1 is formed on the upper portion thereof, and a drain region (n-type impurity) is formed on the inner surface of the p-type well 1. A region: 2), a channel region 11, and a source region (n-type impurity region: 3) are formed. In addition, on the channel 11, a bottom silicon oxide film 4, a SiN film 5 serving as a charge storage layer, a top silicon oxide film 6, and a control gate electrode 7 are sequentially stacked. have. Each channel region 11 of adjacent cells is electrically separated from the device isolation region 10.
    [44] In a MONOS type memory cell having such a structure, charge is injected into the SiN film 5 serving as the gate insulating film to trap charge at the charge trapping center position, or the trapped charge is discharged from the SiN film so as to release the threshold of the cell. It is controlled to have a memory function.
    [45] In a nonvolatile memory having a MONOS type memory cell, writing, erasing, and reading are performed as follows (where "write" means injecting electrons into the SiN film, and "erasing" means electrons from the SiN film). Corresponding to each emitting).
    [46] First, as a writing method, as shown in FIG. 16, by applying a write potential (+ Vpg) to the control gate electrode 7, the well region 1, the source region 3, and the drain region 2 are grounded. A high electric field is applied to the SiN film 5 to inject electrons into the SiN film 5 by Fowler-Nordheim (FN).
    [47] As the erase method, as shown in FIG. 17, a negative erase potential (-Veg) is applied to the control gate 7 and a positive potential (+ Vew) is applied to the well 1, and the SiN film is applied. By applying a high electric field to (5), electrons in the SiN film 5 are FN tunneled to the semiconductor substrate 9 side.
    [48] However, when a conventional MONOS type memory cell is used for a nonvolatile semiconductor memory device, the following three problems exist.
    [49] First, when forming the gate insulating film, the bottom silicon oxide film 4, the SiN film 5, and the top silicon oxide film 6 were formed after the device isolation region 10 was formed.
    [50] For this reason, as shown in FIG. 18, the SiN film 5 as a charge storage layer is not only formed on the channel region 11, but is formed on the element isolation region 10 as well. In this manner, when the charge storage layer is formed to extend from the channel region to the device isolation region, even if charge is injected into the charge storage layer on the channel region by writing, it is caused by a magnetic field and a thermal excitation phenomenon. The diffusion of charge in the charge accumulation layer occurs and charge moves from the channel region toward the device isolation region.
    [51] This charge transfer reduces the amount of charge on the channel and degrades the charge retention characteristics of the cell. In order to suppress the occurrence of such a phenomenon, as shown in FIG. 19, it is also conceivable to provide the isolation region 12 on the element isolation region 10 and to separate the SiN film 5 as the charge storage layer.
    [52] However, even with such a method, the SiN film 5 does not only enter the channel region 11 but also has a portion 13 protruding to the device isolation region 10 to sufficiently improve the charge retention characteristics. Could not.
    [53] In addition, when a matrix cell array formed of word lines and bit lines is formed in a MONOS cell that writes and erases through an FN tunnel, a selection transistor is required to prevent writing.
    [54] As shown in Fig. 20, in the NOR cell array, one memory cell transistor MT1 and two select transistors ST1 and ST2 are required for each memory cell MC1.
    [55] In the NAND cell array, as shown in Fig. 21, memory cell transistors MT11 to MT1n (n is an integer of 1 or more) and two selection transistors ST11 and ST12 connected in series for each memory cell MC11 are required.
    [56] Comparing these, the number of the selection transistors for the memory cell transistors is advantageous in miniaturization since the NAND type is smaller.
    [57] Here, the following second problem exists in forming the gate insulating film of the selection transistor.
    [58] The memory cell and the select transistor are formed adjacent in the cell array. Conventionally, the memory cell and the selection transistor have the same configuration without making the gate insulating film different. For this reason, the gate insulating film of the selection transistor included the charge storage layer similarly to the memory cell, the threshold value of the selection transistor was changed, and the read operation of the memory cell was unstable.
    [59] Third, in the transistors arranged in the peripheral region of the cell array, there are transistors requiring high breakdown voltage, and transistors not requiring high breakdown voltage and requiring high driving capability. Conventionally, since the same gate insulating film was used for a peripheral transistor, a thick insulating film was formed in accordance with a transistor requiring high breakdown voltage. As a result, even in transistors requiring high-speed operation, the threshold value is set low, so that the driving capability cannot be increased, resulting in a decrease in operating speed.
    [60] SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of achieving an improvement in charge retention characteristics, stabilization of a read operation using a selection transistor, and an improvement in the operation speed of a peripheral transistor.
    [1] BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a longitudinal sectional view showing a cross section of an element of one step in a method of manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.
    [2] FIG. 2 is a longitudinal sectional view showing a cross section of an element of one step in a method of manufacturing a nonvolatile semiconductor memory device according to one embodiment; FIG.
    [3] 3 is a longitudinal sectional view showing a cross section of an element of one step in a method of manufacturing a nonvolatile semiconductor memory device according to one embodiment;
    [4] 4 is a longitudinal sectional view showing a cross section of an element of one step in the method of manufacturing a nonvolatile semiconductor memory device according to one embodiment;
    [5] Fig. 5 is a longitudinal sectional view showing a cross section of an element in one step in the method of manufacturing a nonvolatile semiconductor memory device according to one embodiment.
    [6] 6 is a longitudinal sectional view showing a cross section of an element in one step of the method for manufacturing a nonvolatile semiconductor memory device according to one embodiment;
    [7] FIG. 7 is a longitudinal sectional view showing a cross-section of an element of one step in the method of manufacturing a nonvolatile semiconductor memory device according to one embodiment. FIG.
    [8] 8 is a longitudinal sectional view showing a cross-section of an element in one step of the method of manufacturing a nonvolatile semiconductor memory device according to one embodiment.
    [9] 9 is a longitudinal sectional view showing a cross section of an element in one step of the method of manufacturing a nonvolatile semiconductor memory device according to one embodiment.
    [10] Fig. 10 is a longitudinal sectional view showing a cross section of an element in one step in the method for manufacturing a nonvolatile semiconductor memory device according to one embodiment.
    [11] FIG. 11 is a longitudinal sectional view showing a cross-section of an element of one step in the method of manufacturing a nonvolatile semiconductor memory device according to one embodiment. FIG.
    [12] 12 is a longitudinal cross-sectional view showing a cross-section of an element of one step in the method of manufacturing a nonvolatile semiconductor memory device according to one embodiment.
    [13] 13 is a longitudinal cross-sectional view showing a cross section of an element in one step and a configuration of the device in a method of manufacturing a nonvolatile semiconductor memory device according to one embodiment.
    [14] Fig. 14 is a longitudinal sectional view showing a configuration around a gate electrode in a conventional nonvolatile semiconductor memory device.
    [15] Fig. 15 is a longitudinal sectional view showing the structure of an element isolation region in a conventional nonvolatile semiconductor memory device.
    [16] 16 is an explanatory diagram showing a writing operation in the conventional nonvolatile semiconductor memory device.
    [17] 17 is an explanatory diagram showing an erase operation in a conventional nonvolatile semiconductor memory device.
    [18] Fig. 18 is an explanatory diagram showing a deterioration mechanism of charge retention characteristics in a conventional nonvolatile semiconductor memory device.
    [19] Fig. 19 is a longitudinal sectional view showing the structure of a conventional nonvolatile semiconductor memory device having improved charge retention characteristics.
    [20] 20 is a circuit diagram showing a configuration of a NOR type array in a MONOS cell.
    [21] Fig. 21 is a circuit diagram showing the structure of a NAND array in a MONOS cell.
    [22] <Explanation of symbols for main parts of drawing>
    [23] 101: p-type semiconductor substrate
    [24] 102: pad oxide film
    [25] 103, 107, 114, 143, 151, 152: resist film
    [26] 104: n-type well
    [27] 105: p-type well
    [28] 111: bottom oxide film
    [29] 112: SiN film
    [30] 113: first gate oxide film
    [31] 121: second gate oxide film
    [32] 122: HTO film
    [33] 123, 133: polycrystalline silicon film
    [34] 124 silicon nitride film
    [35] 125: silane oxide film
    [36] 131, 132: silicon oxide film
    [37] 141: WSi membrane
    [38] 142: TEOS oxide film
    [39] 150: saw oxide film
    [61] A nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate, a first transistor including a first gate insulating film and a first gate electrode formed on a surface of the semiconductor substrate, and a second gate insulating film formed on a surface of the semiconductor substrate. And a second transistor including a second gate electrode, wherein the first gate insulating layer includes a charge accumulation layer, and the second gate insulating layer does not include a charge accumulation layer, and the first transistor and the second transistor are included. The transistor is device-separated by a trench, and the charge accumulation layer in the first transistor is present only in the device region.
    [62] The first gate insulating film includes a bottom silicon oxide film having a film thickness of 1 nm or more and 10 nm or less, a silicon nitride film as the charge storage layer having a film thickness of 0.5 nm or more and 7 nm or less, and a top silicon oxide film having a film thickness of 5 nm or more and 15 nm or less. The thickness of the bottom silicon oxide film may be thinner than that of the top silicon oxide film.
    [63] Alternatively, the first gate insulating film has a bottom silicon oxide film having a film thickness of 1 nm or more and 10 nm or less, a tantalum oxide film as the charge storage layer, and a top silicon oxide film having a film thickness of 5 nm or more and 15 nm or less, and the bottom silicon oxide film. May be thinner than the film thickness of the top silicon oxide film.
    [64] Alternatively, the first gate insulating film may include a bottom silicon oxide film having a thickness of 1 nm or more and 10 nm or less, a strontium titanate film or a barium strontium titanate film as the charge storage layer, and a top silicon oxide film having a thickness of 5 nm or more and 15 nm or less. The thickness of the bottom silicon oxide film may be thinner than that of the top silicon oxide film.
    [65] The nonvolatile semiconductor memory device has a cell array, the cell array has the first transistor as a cell transistor and the second transistor as a selection transistor, and the second gate insulating film in the second transistor has a film thickness. It is also possible to have a silicon oxide film having a thickness of 5 nm or more and 15 nm or less.
    [66] The nonvolatile semiconductor memory device includes a peripheral transistor in a peripheral region of the cell array, and the peripheral transistor includes a first peripheral transistor including a third gate insulating layer and a third gate electrode formed on a surface of the semiconductor substrate; A second peripheral transistor including a fourth gate insulating film and a fourth gate electrode formed on the surface of the semiconductor substrate may be provided, and the third gate insulating film and the fourth gate insulating film may have different film thicknesses.
    [67] A method of manufacturing a nonvolatile semiconductor memory device of the present invention is a method of manufacturing a device having a cell array including a cell transistor and a selection transistor, the method comprising: a charge storage layer as a gate insulating film for the cell transistor on a surface of a semiconductor substrate; Forming a first gate insulating film; forming a second gate insulating film containing no charge storage layer as a gate insulating film for the selection transistor on a surface of the semiconductor substrate; and a device in which the cell transistor is formed. And forming a trench between the region and the element region where the selection transistor is formed, to perform element isolation, wherein the charge accumulation layer in the cell transistor is present only in the element region.
    [68] Further, the manufacturing method of the present invention is a method of manufacturing a device having a cell array including a cell transistor and a selection transistor, and a peripheral circuit including a peripheral transistor, wherein the gate insulating film for the cell transistor is formed on a surface of a semiconductor substrate. Forming a first gate insulating film including a charge storage layer, forming a second gate insulating film containing no charge storage layer as a gate insulating film for the selection transistor on a surface of the semiconductor substrate, and the semiconductor Forming, as a gate insulating film for the peripheral transistor, a third gate insulating film containing no charge storage layer on the surface of the substrate, an element region in which the cell transistor is formed, an element region in which the selection transistor is formed, Trench between device regions in which the peripheral transistor is formed And forming the second gate insulating film and forming the third gate insulating film at the same time. The charge storage layer in the cell transistor is formed in the device region. It is characterized in that it is made to exist only.
    [69] Or the manufacturing method of this invention is a manufacturing method of the apparatus which has a cell array containing a cell transistor and a selection transistor, and a peripheral circuit containing a 1st peripheral transistor and a 2nd peripheral transistor, Comprising: Forming a first gate insulating film including a charge storage layer as a gate insulating film for a cell transistor, and a second gate insulating film containing no charge storage layer as a gate insulating film for the selection transistor on a surface of the semiconductor substrate. Forming a third gate insulating film on the surface of the semiconductor substrate, the third insulating film including no charge storage layer as a gate insulating film for the first peripheral transistor, and forming a second peripheral film on the surface of the semiconductor substrate. The gate insulating film for the transistor does not include a charge storage layer and is Forming a fourth gate insulating film that is thinner than the three gate insulating film, an element region in which the cell transistor is formed, an element region in which the selection transistor is formed, and an element region in which the first and second peripheral transistors are formed Forming a trench between the elements, and separating the elements; forming the second gate insulating film and forming the third gate insulating film are performed simultaneously, and the charge accumulation layer in the cell transistor. Is characterized by being present only in the element region.
    [70] The first and second gate insulating layers may include an HTO layer as an uppermost layer.
    [71] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
    [72] The structure and manufacturing method of the MONOS type nonvolatile semiconductor memory device having the NAND type cell array structure according to the present embodiment will be described with reference to FIGS.
    [73] In this embodiment, as the gate oxide film of the peripheral transistor, an oxide film having two kinds of film thicknesses, a thick gate oxide film of HV (High Voltage) system and a thin gate oxide film of LV (Low Voltage) system, is formed, and the HV gate is formed. The same oxide film as the oxide film is formed as the gate oxide film of the selection transistor in the cell array.
    [74] As shown in Fig. 1, the pad oxide film 102 is formed and patterned on the p-type semiconductor substrate 101 by, for example, thermal oxidation.
    [75] A deep n-type well 104 is formed by implanting phosphorus as an n-type impurity so as to have a desired depth and impurity profile on the surface portion of the semiconductor substrate 101 using the resist film 103. The p-type well 105 is formed in the surface portion of the n-type well 104 so that boron as a p-type impurity has a desired depth and impurity concentration.
    [76] The resist film 103 is removed to form a resist film 107 as shown in FIG. 2, and n-type impurities are ion implanted to form an n-type well 106 in the outer peripheral portion of the p-type well 105. .
    [77] As shown in FIG. 3, the pad oxide layer 102 is removed. The silicon oxide film serving as the bottom oxide film 111 of the memory cell is formed to have a thickness of 3 nm by thermal oxidation, for example, and the SiN film 112 serving as a charge storage layer of the memory cell is described. For example, it deposits in the film thickness of 0.5 nm-3 nm. At this time, in order to improve the reliability of the bottom oxide film, it may be nitrided with N 2 O or NH 3 to oxynitride.
    [78] The resist is applied to the entire surface, the peripheral region and the formation region of the selection transistor in the cell array are opened, and a development process is performed so as to cover the cell formation portion, thereby patterning the resist to form a resist film 151. Reactive ion etching (RIE) is performed on the SiN film 112 by using the resist film 151 as a mask to remove portions at the openings. This processing leaves the SiN film 112 only in the cell formation portion.
    [79] 4 is a longitudinal cross section of an element in the cell array, and a portion where the resist film 113 is opened is a region for forming a selection transistor. After the resist film 112 is peeled off, the bottom oxide film 111 in the opening portion is removed by wet etching. Then, a first gate oxidation process is performed using a thermal oxidation method, and the surface of the substrate 101 is oxidized to form the first gate oxide film 113 with a film thickness of, for example, 5 nm. At this time, the substrate surface in the cell formation portion where the SiN film 112 remains is not oxidized.
    [80] As shown in Fig. 5, a resist is applied to pattern the resist film 114 so as to remove a region forming an LV gate oxide film in the peripheral region. Using the resist film 114 as a mask, wet etching is performed to remove the first gate oxide film 113 on the formation region of the LV transistor.
    [81] After the resist film 114 is removed, a wet process is performed on the entire surface of the wafer to wet etch the first gate oxide film 113 by about 1 to 2 nm.
    [82] As shown in Fig. 6, a second gate oxidation process is performed by thermal oxidation, and the substrate is oxidized to form a second gate oxide film 121 having a thickness of 2 nm on the formation region of the LV transistor. The top oxide film 150 is formed on the SiN film 112 by depositing an HTO (High Temperature Oxide) film 122 on the entire surface, for example, at a film thickness of 5 nm.
    [83] Subsequently, in order to increase the density of the HTO film 122, further annealing treatment or heat treatment such as an oxidation process or oxynitride by nitriding with N 2 O or NH 3 improves the reliability of the gate insulating film. You can.
    [84] As shown in FIG. 7, a polycrystalline silicon film 123 serving as a gate electrode is deposited. Here, the gate oxide film of the HV transistor in the peripheral region, the gate oxide film of the selection transistor in the memory cell region, and the silicon oxide film in which the first gate oxide film 113 and the second gate oxide film 121 are stacked, and the HTO film. It consists of a laminated oxide film with 122.
    [85] On the other hand, the gate oxide film of the LV transistor in the peripheral region is composed of a laminated oxide film of the second gate oxide film 121 and the HTO film 122.
    [86] Here, by making the top oxide film thicker than the bottom oxide film, it is possible to cause the phenomenon that the charge injected into the charge storage layer moves during writing / erasing more easily on the bottom oxide film side.
    [87] Next, the process of forming the active region will be described with reference to FIGS. 7 to 13 showing the isolation of elements in the memory cell portion.
    [88] As shown in Fig. 7, a silicon nitride film 124 is deposited on the polycrystalline silicon film 123 with a film thickness of 70 nm so as to be a mask material during etching for forming a trench on the substrate surface. On the silicon nitride film 124, a TEOS-based or silane-based oxide film 125 is deposited at a film thickness of 200 nm, and a resist is applied on the surface thereof. The resist film 152 is formed to cover the active region, and the device isolation region is removed.
    [89] Using the resist film 152 as a mask, the silicon oxide film 125 and the silicon nitride film 124 as mask materials are etched and removed from above in accordance with the RIE method. Thereafter, the resist film 152 is removed. Accordingly, the pattern of the active region is transferred from the resist film 152 to the silicon oxide film 125 and the silicon nitride film 124.
    [90] As shown in Fig. 8, the laminated film of the silicon oxide film 125 and the silicon nitride film 124 is used as a hard mask, so that the polycrystalline silicon film 123 serving as a gate, the gate oxide film in the memory cell region, and the peripheral region The gate oxide film of the HV transistor, the gate oxide film of the LV transistor, and the semiconductor substrate 101 are etched to a depth of about 200 nm from the surface of the substrate by the RIE method to form a trench 126 for device isolation. At this time, the boundary region of the memory cell and the selection transistor is set between the memory cell and the selection transistor on the active region.
    [91] As shown in Fig. 9, thermal oxidation is performed on the semiconductor substrate 101 to form a silicon oxide film 131 having a film thickness of, for example, 3 nm to 6 nm. This silicon oxide film 131 is formed to protect the semiconductor substrate 101.
    [92] A silicon oxide film 132 serving as a buried material of the trench 126 is deposited over the entire surface. As the deposition method, for example, a TEOS oxide film may be deposited by CVD, or a silane oxide film may be deposited by HDP (High Density Plasma), or the silicon oxide film may be deposited from the trench 126 of the semiconductor substrate 101. It deposits on conditions to fully fill up to (125). 9 shows a state in which the silicon oxide film 132 is embedded by the HDP method.
    [93] Next, as shown in FIG. 10, the silicon oxide film 132 is polished and planarized by a chemical mechanical polishing (CMP) method. In this polishing step, the silicon nitride film 124 becomes a polishing stopper.
    [94] After that, high temperature annealing is performed at 900 ° C. or higher to release the stress generated by the embedding of the trench 126.
    [95] Subsequently, a wet treatment using a buffered HF or the like is performed to remove the micro scratches on the surface of the silicon oxide film 126 embedded in the trenches and lift off foreign matter adhered during polishing.
    [96] As shown in FIG. 11, the silicon nitride film 124 is removed by wet etching with hot phosphoric acid. Further, the corner 126a of the buried silicon oxide film 132 of the trench 126 is rounded by wet etching. And the polycrystal silicon film 133 into which phosphorus used as a gate wiring was introduce | transduced is deposited by the film thickness of 70 nm, for example.
    [97] Thereafter, a thermal process is performed at, for example, 850 ° C. for 30 minutes to diffuse impurities from the polycrystalline silicon film 133 to the polycrystalline silicon film 123.
    [98] Next, a tungsten silicide (WSi) film 141 is deposited on the polycrystalline silicon film 133 with a film thickness of 50 nm, for example, and the TEOS oxide film 142 serving as a mask material for processing the gate electrode is formed. For example, it deposits by the CVD method with a film thickness of 200 nm.
    [99] Thereafter, as shown in FIG. 12, a resist is applied to develop the pattern on the gate electrode, and the pattern is transferred to the TEOS oxide film 142 as a mask material using the obtained resist film 143. 12 shows a gate cross section in the cell array, in which the region in which the SiN film 112 serving as the charge storage layer is present is a region in which a memory cell is formed, and the region in which no region exists is a region in which a select transistor is formed.
    [100] The resist film 143 is removed, and the WSi film 141 and the polycrystalline silicon films 133 and 123 are etched using the TEOS oxide film 142 as a mask. The gate insulating film is etched by RIE to remove the top oxide film 150 and SiN film 112 of the cell. At this time, etching is performed under the condition of leaving the gate insulating film of the selection transistor.
    [101] Thereafter, post-oxidation is performed, and ion implantation of impurities is performed to form a diffusion layer serving as a drain and a source not shown in the memory cell or the peripheral transistor. Further, an interlayer insulating film made of BPSG or the like not shown is formed. A contact hole is formed on the surface of the gate electrode or the diffusion layer with respect to the interlayer insulating film, and a conductive material is embedded to form a contact to the gate electrode or the diffusion layer. A wiring layer is formed using a metal material or the like on the interlayer insulating film, and a passivation layer is formed on the surface thereof to complete the manufacturing process.
    [102] According to the above embodiment, the SiN film 112 as the charge storage layer in the gate insulating film in the memory cell is formed only on the channel region of the cell, and not on the device isolation region. As a result, the phenomenon of charge transfer from the charge accumulation layer on the channel of the cell transistor to the charge accumulation layer on the element isolation region does not occur, which is a problem in the charge retention characteristic, thereby obtaining good charge retention characteristics.
    [103] In addition, unlike the gate insulating film of the cell transistor, the gate insulating film of the selection transistor is formed only of the silicon oxide film (the first gate oxide film 113, the second gate oxide film 121, and the HTO film 122) that does not include the charge storage layer. As a result, the threshold value of the selection transistor does not change, enabling stable read operation.
    [104] In addition, by forming two gate oxide films having different film thicknesses in the peripheral transistors, a thick gate oxide film (first gate oxide film 113, second gate oxide film 121, and HTO) is required for an HV transistor that requires high breakdown voltage in the gate oxide film. The film 122 is formed and a thin gate oxide film (second gate oxide film 121 and HTO film 122) is used for an LV transistor that does not require high breakdown voltage and requires high driving capability. Performance improvement, etc. can be aimed at.
    [105] The above-described embodiments are examples and do not limit the present invention. For example, the above embodiment uses a WSi polyside structure in which a WSi film and a polycrystalline silicon film are laminated on a gate wiring. However, not only this material but also the silicide of the diffusion layer, the gate wiring, and Ti or Co can be formed, and the cells and peripheral transistors can be salicided.
    [106] As described above, according to the nonvolatile semiconductor memory device and the method of manufacturing the same, the charge accumulation layer required in the gate insulating film of the cell transistor is formed so as not to protrude from the channel region of the cell to the element isolation region. The phenomenon of movement of charge from the charge accumulation layer of the phase to the device isolation region does not occur, and the charge retention characteristic is improved.
    [107] In addition, unlike the gate insulating film of the cell transistor, the gate insulating film of the selection transistor is formed without including the electrode accumulation layer, so that the threshold value of the selection transistor does not change and the read operation is stabilized.
    [108] Also, in the peripheral transistors, a thick gate oxide film is formed in a transistor requiring a high breakdown voltage in the gate oxide film, and a thin gate oxide film is formed in a transistor that does not require high breakdown voltage and requires high driving capability. This is improved.
    权利要求:
    Claims (10)
    [1" claim-type="Currently amended] A semiconductor substrate,
    A first transistor comprising a first gate insulating film formed on a surface of the semiconductor substrate, the first gate insulating film including a charge accumulation layer, and a first gate electrode;
    A second transistor including a second gate insulating film formed on a surface of the semiconductor substrate, the second gate insulating film not including a charge storage layer, and a second gate electrode
    Including,
    And the first transistor and the second transistor are separated by trenches, and the charge accumulation layer in the first transistor exists only in the element region.
    [2" claim-type="Currently amended] The method of claim 1,
    The first gate insulating film includes a bottom silicon oxide film having a film thickness of 1 nm or more and 10 nm or less, a silicon nitride film as the charge storage layer having a film thickness of 0.5 nm or more and 7 nm or less, and a film thickness of 5 nm or more and 15 nm. Including the top silicon oxide film which is the following,
    The film thickness of the bottom silicon oxide film is thinner than the film thickness of the top silicon oxide film.
    [3" claim-type="Currently amended] The method of claim 1,
    The first gate insulating film includes a bottom silicon oxide film having a film thickness of 1 nm or more and 10 nm or less, a tantalum oxide film as the charge storage layer, and a top silicon oxide film having a film thickness of 5 nm or more and 15 nm or less,
    The film thickness of the bottom silicon oxide film is thinner than the film thickness of the top silicon oxide film.
    [4" claim-type="Currently amended] The method of claim 1,
    The first gate insulating film includes a bottom silicon oxide film having a film thickness of 1 nm or more and 10 nm or less, a strontium titanate film or barium strontium titanate film as the charge storage layer, and a top silicon oxide film having a film thickness of 5 nm or more and 15 nm or less. and,
    The film thickness of the bottom silicon oxide film is thinner than the film thickness of the top silicon oxide film.
    [5" claim-type="Currently amended] The method according to any one of claims 1 to 4,
    The nonvolatile semiconductor memory device has a cell array,
    The cell array includes the first transistor as a cell transistor and the second transistor as a select transistor,
    The second gate insulating film of the second transistor includes a silicon oxide film having a thickness of 5 nm or more and 15 nm or less.
    [6" claim-type="Currently amended] The method of claim 5,
    The nonvolatile semiconductor memory device includes a peripheral transistor in a peripheral region of the cell array,
    The peripheral transistor,
    A first peripheral transistor including a third gate insulating film and a third gate electrode formed on a surface of the semiconductor substrate;
    A second peripheral transistor including a fourth gate insulating layer and a fourth gate electrode formed on a surface of the semiconductor substrate
    Including,
    And the third gate insulating film and the fourth gate insulating film have different film thicknesses.
    [7" claim-type="Currently amended] A method of manufacturing a nonvolatile semiconductor memory device having a cell array including a cell transistor and a selection transistor, the method comprising:
    Forming a first gate insulating film including a charge storage layer as said gate insulating film for cell transistors on a surface of a semiconductor substrate;
    Forming a second gate insulating film containing no charge storage layer as the gate insulating film for the selection transistor on a surface of the semiconductor substrate;
    Forming a trench between the device region where the cell transistor is formed and the device region where the selection transistor is formed to perform device isolation.
    Including,
    And wherein said charge storage layer in said cell transistor is configured to exist only in said element region.
    [8" claim-type="Currently amended] A method of manufacturing a nonvolatile semiconductor memory device having a cell array including a cell transistor and a selection transistor, and a peripheral circuit including a peripheral transistor,
    Forming a first gate insulating film including a charge storage layer as said gate insulating film for cell transistors on a surface of a semiconductor substrate;
    Forming a second gate insulating film containing no charge storage layer as the gate insulating film for the selection transistor on a surface of the semiconductor substrate;
    Forming, as a gate insulating film for the peripheral transistor, a third gate insulating film containing no charge storage layer on the surface of the semiconductor substrate;
    Forming a trench between the device region where the cell transistor is formed, the device region where the selection transistor is formed, and the device region where the peripheral transistor is formed, and performing device isolation.
    Including,
    The step of forming the second gate insulating film and the step of forming the third gate insulating film are performed at the same time, and the charge storage layer in the cell transistor is configured to exist only in the element region. Method of manufacturing a semiconductor memory device.
    [9" claim-type="Currently amended] A method of manufacturing a nonvolatile semiconductor memory device having a cell array including a cell transistor and a selection transistor, and a peripheral circuit including a first peripheral transistor and a second peripheral transistor,
    Forming a first gate insulating film including a charge storage layer as said gate insulating film for cell transistors on a surface of a semiconductor substrate;
    Forming a second gate insulating film containing no charge storage layer as the gate insulating film for the selection transistor on a surface of the semiconductor substrate;
    Forming, as a gate insulating film for the first peripheral transistor, a third gate insulating film containing no charge storage layer on the surface of the semiconductor substrate;
    Forming a fourth gate insulating film on the surface of the semiconductor substrate as the gate insulating film for the second peripheral transistor, wherein the fourth gate insulating film does not include a charge storage layer and is thinner than the third gate insulating film;
    Forming a trench between the device region where the cell transistor is formed, the device region where the selection transistor is formed, and the device region where the first and second peripheral transistors are formed, and performing device isolation.
    Including,
    The step of forming the second gate insulating film and the step of forming the third gate insulating film are performed at the same time, and the charge storage layer in the cell transistor is configured to exist only in the element region. Method of manufacturing a semiconductor memory device.
    [10" claim-type="Currently amended] The method according to any one of claims 7 to 9,
    And the first and second gate insulating films comprise a high temperature oxide (HTO) film as the uppermost layer.
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    同族专利:
    公开号 | 公开日
    US20020033501A1|2002-03-21|
    JP4346228B2|2009-10-21|
    TW525170B|2003-03-21|
    CN1187831C|2005-02-02|
    US20050285219A1|2005-12-29|
    KR100402670B1|2003-10-22|
    CN1345092A|2002-04-17|
    JP2002100686A|2002-04-05|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-09-21|Priority to JPJP-P-2000-00287084
    2000-09-21|Priority to JP2000287084A
    2001-09-14|Application filed by 니시무로 타이죠, 가부시끼가이샤 도시바
    2002-03-28|Publication of KR20020023116A
    2003-10-22|Application granted
    2003-10-22|Publication of KR100402670B1
    优先权:
    申请号 | 申请日 | 专利标题
    JPJP-P-2000-00287084|2000-09-21|
    JP2000287084A|JP4346228B2|2000-09-21|2000-09-21|Nonvolatile semiconductor memory device and manufacturing method thereof|
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